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FPGA STUFF

This page is about my interest in FPGA design. It is sooo much fun!

2026-08-15: Tristate Buffers with Yosys and Gatemate

Recently, I ran into the problem of dealing with tristate buffers on my Olimex GateMateA1-EVB board. For some reason, Yosys did not like it when I wrote code like this:

module toplevel( inout logic tristate_io);
    logic tristate_input;
    logic tristate_output;
    logic tristate_o0i1;
    assign tristate_input=tristate_io;
    assign tristate_io=(tristate_o0i1)?1'bz:tristate_output;    // THIS IS THE WRONG WAY
    submodule SUBMODULE(
        .tristate_input    (tristate_input),
        .tristate_output   (tristate_output),
        .tristate_o0i1     (tristate_o0i1)
    );
endmodule

A couple of experiments later, I found out that the proper way to do it was to make us of the Primitives Library:

module toplevel( inout logic tristate_io);
    logic tristate_input;
    logic tristate_output;
    logic tristate_o0i1;
//    assign tristate_input=tristate_io;
//    assign tristate_io=(tristate_o0i1)?1'bz:tristate_output;    // THIS IS THE WRONG WAY
    CC_TRIBUF cc_tribuf0( .A(tristate_input), .T(tristate_o0i1), .Y(tristate_outout), IO(tristate_io)); // This is the better way
    submodule SUBMODULE(
        .tristate_input    (tristate_input),
        .tristate_output   (tristate_output),
        .tristate_o0i1     (tristate_o0i1)
    );
endmodule

That solved my problem!